Mrs. D. Tejaswi | ANITS, Visakhapatnam
RTL is a symbolic notation used to describe the micro-operations performed on the data stored in registers. It uses symbols like R1 ← R2 to denote that the content of R2 is transferred to R1. It forms the basis for designing and understanding digital systems at the register level.
Register transfer involves moving binary data from one register to another. It is controlled by clock pulses and conditional signals. Example: If (P=1) then R2 ← R1 means transfer occurs only when control signal P is active.
A bus is a shared communication path that connects multiple registers. Using multiplexers, a common bus can be shared by all registers. Memory transfers use the MAR (Memory Address Register) and MBR (Memory Buffer Register) to read/write data: MBR ← M[MAR] for a read operation.
These include addition, subtraction, increment, decrement, and complement operations on binary data stored in registers. Example: R3 ← R1 + R2 (addition), R2 ← R2 + 1 (increment). These are performed by the ALU.
Bitwise logical operations — AND, OR, XOR, NOT — applied to register contents. They are used for masking, setting, clearing, or inverting specific bits. Example: R1 ← R1 AND R2 clears bits in R1 where R2 has 0s.
Shift operations move bits left or right within a register. Types: Logical shift (fills with 0), Arithmetic shift (preserves sign bit), Circular/Rotate shift (bits wrap around). Used in multiplication, division, and serial data transfer.
The ALSU is a combined hardware unit that performs all arithmetic, logic, and shift microoperations. It is controlled by selection lines that determine which operation to execute. The output is then stored back into a register.
An instruction code is a binary code that directs the computer to perform a specific operation. It consists of an operation code (opcode) specifying the operation and an address field specifying the operand location. The opcode determines what action the CPU performs.
Key registers include: PC (Program Counter) — holds the address of the next instruction; AC (Accumulator) — stores intermediate results; IR (Instruction Register) — holds the current instruction; MAR — memory address register; MBR/MDR — memory data register; SP — stack pointer.
Instructions are classified as memory-reference (operand in memory), register-reference (operate on AC without memory), and I/O instructions (for input/output). Each has a distinct format defined by the opcode bits and mode bit (direct/indirect addressing).
In a hardwired control unit, the control signals are generated by logic circuits (flip-flops, gates, decoders). It is fast but inflexible — changing the instruction set requires redesigning the hardware. Suitable for RISC processors where simplicity is preferred.
The instruction cycle consists of: Fetch (get instruction from memory using PC), Decode (interpret the opcode), Execute (perform the operation). Some instructions also have an indirect cycle (for indirect addressing) and an interrupt cycle.
These instructions use memory as the source or destination of data. Examples include AND (AC ← AC AND M[EA]), ADD (AC ← AC + M[EA]), LDA (load AC from memory), STA (store AC to memory), BUN (branch unconditionally), and BSA (branch and save return address).
In microprogrammed control, control signals are stored as microinstructions in a special memory called Control Memory (CM) or Control Store. Each microinstruction contains bits that directly activate the control lines of the datapath.
The Control Address Register (CAR) holds the address of the next microinstruction. Address sequencing methods include: incrementing CAR, unconditional branch, conditional branch, and mapping from instruction opcode to microprogram address using a mapping ROM.
Microinstructions can be horizontal (wide word, many control bits, high parallelism), vertical (narrow word, encoded fields, less parallelism), or diagonal (a compromise). Each format trades hardware cost against flexibility and execution speed.
A microprogram is a sequence of microinstructions that implements a machine instruction. The control unit is designed by writing microprograms for each instruction and storing them in control memory. The fetch cycle is a common microprogram shared by all instructions.
Instead of a single accumulator, a general register organization uses a set of CPU registers (R0–Rn) connected via an internal bus to an ALU. A multiplexer selects the source registers (A and B) for the ALU, and a decoder selects the destination register for storing the result. This improves speed and flexibility.
Instruction formats define how bits are divided among opcode, address fields, and mode. Common formats: Three-address (opcode, dest, src1, src2), Two-address, One-address (accumulator-based), Zero-address (stack-based, uses push/pop). Longer formats allow more flexibility but need wider instruction registers.
Addressing modes specify how to calculate the effective address (EA) of the operand. Types: Immediate (operand = constant), Direct (EA = address field), Indirect (EA = M[address]), Register, Register Indirect, Displacement/Indexed (EA = base + index), Relative (EA = PC + offset), Autoincrement/Autodecrement.
Data transfer instructions move data between registers and memory (MOV, LOAD, STORE, PUSH, POP). Data manipulation instructions perform arithmetic (ADD, SUB, MUL, DIV), logical (AND, OR, NOT, XOR), and shift operations on data.
Program control instructions alter the sequential flow: unconditional branch (JMP), conditional branch (BEQ, BNE, BGT), subroutine call (CALL/JSR) and return (RET), software interrupt (INT), and return from interrupt (IRET). These enable loops, decisions, and function calls.
A stack is a LIFO (Last In First Out) data structure. A hardware stack is a set of memory locations with a Stack Pointer (SP). PUSH decrements SP and stores data; POP reads data and increments SP. Stacks are used for subroutine return addresses, expression evaluation, and parameter passing.
RISC (Reduced Instruction Set Computer): few, simple instructions, fixed-length encoding, load/store architecture, hardwired control, many registers — e.g., MIPS, ARM. CISC (Complex Instruction Set Computer): many complex instructions, variable-length encoding, memory-to-memory operations, microprogrammed control — e.g., x86. RISC favors pipelining; CISC reduces instruction count per program.
Memory is organized in a hierarchy based on speed and cost: Registers → Cache → Main Memory (RAM) → Secondary Storage (HDD/SSD) → Tertiary (optical/tape). Faster memory is smaller and more expensive; slower memory is larger and cheaper. The hierarchy exploits locality of reference for performance.
Main memory (RAM) is directly accessible by the CPU. It is organized as an array of storage cells, each holding one bit, grouped into bytes or words. Types: SRAM (fast, used in cache), DRAM (slower, denser, used in main memory). Memory chips are connected via address, data, and control buses.
Auxiliary (secondary) memory provides large, non-volatile storage. Includes hard disk drives (HDD), solid-state drives (SSD), magnetic tapes, and optical disks. Data is transferred to/from main memory as needed. Access is much slower than RAM but far cheaper per bit.
Associative memory is accessed by content rather than by address. A search key is compared simultaneously with all stored words, and matching entries are flagged. Used in TLBs (Translation Lookaside Buffers) and cache tag stores for fast lookups.
Cache is a small, fast memory between CPU and main memory. It stores frequently accessed data (principle of locality). Mapping techniques: Direct mapping (each block maps to one cache line), Fully associative (any block in any line), Set-associative (compromise). Replacement policies: LRU, FIFO, Random. Write policies: Write-through, Write-back.
Virtual memory allows programs to use more memory than physically available by storing parts of a process on disk. The OS manages a page table to map virtual addresses to physical addresses. Page faults trigger loading of the required page from disk. Techniques: Paging, Segmentation, Segmentation with Paging.
Peripheral devices include input devices (keyboard, mouse, scanner), output devices (monitor, printer), and storage devices (disk drives). They communicate with the CPU via I/O interfaces that handle speed and format differences between the CPU and peripherals.
An I/O interface (I/O controller) bridges the CPU and peripherals. It contains data registers, status registers, and control registers. The CPU communicates via I/O ports using addresses. Interfaces handle data buffering, format conversion, and timing differences.
In asynchronous transfer, sender and receiver operate at different speeds and use handshaking signals to synchronize. Strobe method: sender asserts a strobe signal to indicate valid data. Handshaking: uses Request (RQ) and Acknowledge (ACK) signals for a two-way synchronization protocol.
Three main I/O transfer modes: (1) Programmed I/O — CPU continuously polls the device status (busy-wait). (2) Interrupt-driven I/O — device interrupts CPU when ready, CPU handles ISR. (3) DMA — device transfers data directly to/from memory without CPU involvement, only notifying CPU when done.
When multiple devices request interrupts simultaneously, a priority scheme determines which is serviced first. Methods: Daisy chaining (hardware priority — device closest to CPU gets highest priority), Parallel priority (each device has a separate interrupt line), Software polling (CPU checks each device in order).
DMA allows peripherals to transfer data directly to/from memory, bypassing the CPU. A DMA controller manages the transfer. CPU provides start address, block size, and direction, then releases the bus. DMA uses cycle stealing or burst mode. Ideal for bulk data transfers (disk, network) to free the CPU for computation.
1. Which register holds the address of the next instruction to be executed?
2. In a hardwired control unit, control signals are generated by:
3. Which addressing mode adds a constant offset to the Program Counter to find the effective address?
4. Cache memory mapping where each main memory block maps to exactly one cache line is called:
5. DMA (Direct Memory Access) is primarily used to:
6. Which of the following is a characteristic of RISC architecture?
7. Associative memory (Content Addressable Memory) is accessed by:
8. In interrupt-driven I/O, the CPU is interrupted by a device when:
9. The shift microoperation that preserves the sign bit is called:
10. Virtual memory enables programs to use more memory than physically available by: